/* Declarations for PCI-E ECAT new version(id:12345676)

   Author: Golden Wang

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2, or (at your option)
   any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software Foundation,
   Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */

/* File level history (record changes for this file here.
 
   *** Do not include this file in your code. ***

   v 0.1.1 24 Aug 2018 by Golden Wang
     add the definition of host's bar0 offset.

   v 0.1.0 11 May 2018 by Golden Wang
     support SN2401, EEPROM(Spertan6 Flash) and EMG signal.

   v 0.0.0 20 Dec 2016 by Golden Wang
     create, blah blah... */

#ifndef _PCIECAT_H
#define _PCIECAT_H

#define R3600_MODULE_NAME "ixecat_r3600"
#define GENERIC_MODULE_NAME "ixecat_generic"

#define INT_MASK_SHIFT_STOP_BIT  0x10

/* ECAT-M800 SRAM/EEPROM/Flash Reg */
#define SRAM_ECAT_PAGES 2048  // ECAT-M801 8192 Bytes = 2048 Pages(0 ~ 0x7FF) * 4Bytes

//XILINX SP6 Series DUAL Port RAM Register Define
#define REG_COUNT                       0x400
#define REG_COMMAND                     0x404
#define REG_DATA                        0x408
#define REG_STATUS_HOST         0x40C
#define REG_COUNT_CONF          0x410
#define REG_COMMAND_CONF        0x414
#define REG_DATA_CONF           0x418
#define REG_STATUS_DEVICE       0x41C

//XILINX SP6 Series DUAL Port RAM Host Status
#define STA_COMBUSY                     0x00000000      // Command is not ready
#define STA_COMREADY            0x00000001      // Command is ready

//XILINX SP6 Series DUAL Port RAM Response Status
#define STA_COMVALID            0x00000000      // Command Valid
#define STA_ERRCRC                      0x00000100      // CRC Check Error
#define STA_OVERADDRESS         0x00000200      // Over Flash Address Definition
#define STA_ERRCOM                      0x00000300      // Command Error
#define STA_ERRFLASHCTL         0x00000400      // Flash Control Error
#define STA_PCIECHK                     0x00005A00      // PCIe Check Finished
#define STA_BUSY                        0x0000FF00      // Command Busy

//XILINX SP6 Series DUAL Port RAM Command
#define CMD_WRITE                       0xE0000000 //Write Command
#define CMD_READ                        0xF0000000 //Read Command
#define CMD_PAGE_CAL        0x00000001 //Calibration Page Command
#define CMD_PAGE_DEFAULT    0x00000002 //Factory Calibration Page Command

/* CPU Interrupt Register */
#define ISR_ENABLE       0x01	//ISR Reg "En_ISR" for CPU and Host
#define DPRAM_INT_ENABLE 0x02	//ISR Reg "En_RAM" for CPU
#define EMG_INT_ENABLE   0x04	//ISR Reg "En_EMG" for CPU
#define EMG_XOR_ENABLE   0x08	//ISR Reg "En_EMG" for CPU
#define ALL_INT_ENABLE   0x07
#define DPRAM_INT        0x20	//ISR Reg "DPRAM_f" for CPU
#define EMG_INT          0x40	//ISR Reg "EMG_f" for CPU
#define DPRAM_INT_FROM_CPU  0x1ff8	// DPRAM addr 0x1ff8 = 0x7fe * 4

/* Host Interrupt Register */
#define DPRAM_INT_FROM_HOST 0x1ffc	// DPRAM addr 0x1ffc = 0x7ff * 4

/* Signal Index */
#define DPRAM_SIGNAL 0
#define EMG_SIGNAL 1

/* offset of Host/CPU register */
#define SRAM_REGISTER           0x00

/* offset of CPU's register */
#define CPU_ISR_REGISTER	0x00

/* offset of Host's register */
#define EEPROM_REGISTER         		0x00
#define HOST_ISR_REGISTER			0x08
#define GPI_GPO_REGISTER			0x00
#define XAXIS_MODE_REGISTER			0x010
#define XAXIS_COUNTER_REGISTER			0x014
#define YAXIS_MODE_REGISTER			0x018
#define YAXIS_COUNTER_REGISTER			0x01c
#define XAXIS_COUNTER_COMPARE_REGISTER		0x020
#define XAXIS_COUNTER_COMPARE_PULSE_REGISTER	0x024
#define YAXIS_COUNTER_COMPARE_REGISTER		0x028
#define YAXIS_COUNTER_COMPARE_PULSE_REGISTER	0x02c

#define _EEP      EEPROM_REGISTER   //Host's bar0, CPU none
#define _SR       SRAM_REGISTER	    //Host's bar2, CPU's bar0
#define _CPU_ISR  CPU_ISR_REGISTER  //Host   none, CPU's bar1
#define _HOST_ISR HOST_ISR_REGISTER //Host's bar0, CPU none
#define _GPIO     GPI_GPO_REGISTER  //Host's bar1, CPU's bar1
#define _XAXIS_MODE        XAXIS_MODE_REGISTER	  //Host's bar0, CPU none
#define _XAXIS_CNT         XAXIS_COUNTER_REGISTER //Host's bar0, CPU none		
#define _YAXIS_MODE        YAXIS_MODE_REGISTER	  //Host's bar0, CPU none		
#define _YAXIS_CNT         YAXIS_COUNTER_REGISTER //Host's bar0, CPU none		
#define _XAXIS_CNT_CMP     XAXIS_COUNTER_COMPARE_REGISTER //Host's bar0, CPU none	
#define _XAXIS_CNT_CMP_PLS XAXIS_COUNTER_COMPARE_PULSE_REGISTER	//Host's bar0, CPU none
#define _YAXIS_CNT_CMP     YAXIS_COUNTER_COMPARE_REGISTER	//Host's bar0, CPU none	
#define _YAXIS_CNT_CMP_PLS YAXIS_COUNTER_COMPARE_PULSE_REGISTER	//Host's bar0, CPU none

/* mask of registers (32-bit operation) */
#define _SRAM_MASK         0xffffffff
#define _EEP_MASK          0xffffffff
#define _CPU_ISR_MASK      0x0000007f
#define _HOST_ISR_MASK     0x00000001
#define _GPIO_MASK   	   0xffffffff
#define _HOST_INT_CLR_MASK 0xfffffffe
#define _CPU_INT_CLR_MASK  0xfffffffe
#define _32BITS_MASK   	   0xffffffff
#define _HOST_B0_OFF_MASK  0x00000fff
#endif							/* _PCIECAT_H */
