/* Declarations for PCIe-8622

   Author: Winson Chen

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2, or (at your option)
   any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software Foundation,
   Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */

/* File level history (record changes for this file here.
 
   *** Do not include this file in your code. ***
 
   v 0.0.0 22 Sep 2015 by Winson Chen
   create
*/
#ifndef _PCIe8622_H
#define _PCIe8622_H

#define   PCIE86XX_AI_BI_5V     0x0
#define   PCIE86XX_AI_BI_10V    0x1

#define   PCIE86XX_AO_UNI_5V    0       //0  ~  5V
#define   PCIE86XX_AO_BI_5V     1       //+/-   5V
#define   PCIE86XX_AO_UNI_10V   2       //0  ~ 10V
#define   PCIE86XX_AO_BI_10V    3       //+/-  10V

/* IXPCI strcture for read EEPROM */
typedef struct ixpci_eep{
        unsigned long offset;
        unsigned char uBLOCK;           /* 0 Read EEPROM, 1 Recover EEPROM */
        unsigned short count;
        unsigned short read_eep[128];   /* Read EEPROM value */
        float CalAI[2][16];
        float CalAIShift[2][16];
        float CalAO[4][3];
        float CalAOShitf[4][3];
        char AI_ch;                     /* card's AI channel numbers */
        char AO_ch;                     /* card's AO channel numbers */
} ixpci_eep_t;

void calibration(ixpci_eep_t *);
int _set_signal(ixpci_signal_t * sig, ixpci_devinfo_t * dp);

#define MODULE_NAME "ixpcie8622"

/* XILINX SP6 Series DUAL Port RAM Host Status */
#define STA_COMBUSY	0x00000000	// Command is not ready
#define STA_COMREADY	0x00000001	// Command is ready

/* XILINX SP6 Series DUAL Port RAM Register Define */
#define REG_COUNT 		0x400
#define REG_COMMAND		0x404
#define REG_DATA		0x408
#define REG_STATUS_HOST		0x40c
#define REG_COUNT_CONF		0x410
#define REG_COMMAND_CONF	0x414
#define REG_DATA_CONF		0x418
#define REG_STATUS_DEVICE	0x41c

/* XILINX SP6 Serirs DUAL Port RAM Response Status */
#define STA_COMVALID		0x00000000	// Command Valid
#define STA_ERRCRC		0x00000100	// CRC Check Error
#define STA_OVERADDRESS		0x00000200	// Over Flash Address Definition
#define STA_ERRCOM		0x00000300	// Command Error
#define STA_ERRFLASHCTL		0x00000400	// Flash Control Error
#define STA_PCIECHK		0x00005a00	// PCIe Check Finished
#define STA_BUSY		0x0000ff00	// Command Busy

/* XILINX SP6 Series DUAL Port RAM Command */
#define CMD_WRITE		0xe0000000 //Write Command
#define CMD_READ		0xf0000000 //Read Command
#define CMD_PAGE_CAL        	0x00000001 //Calibration Page Command
#define CMD_PAGE_DEFAULT    	0x00000002 //Factory Calibration Page Command

/* The length of the register is 32-bits */

/* offset of registers */ /*MMIO*/
/* bar 0 */
#define	READ_AI_FIFO_DATA	0x00
#define	READ_AI_FIFO_STATUS	0x04
#define	CLEAR_FIFO		0x04	/* Write a 0 to clear data to specified FIFO */
#define	READ_WRITE_AI_INTERNAL_CLOCK_CONTROL_STATUS	0x08
#define	READ_WRITE_AI_MODE_CONTROL_STATUS		0x0C
#define	READ_AI_DATA_LOW	0x10	/* AI channel 0~7 */
#define	AI_SOFTWARE_TRIGGER_CONTROL			0x10 /* Writing a 0 let AI measure AI data.*/
#define	READ_AI_DATA_HIGH	0x14	/* AI channel 8~15 */
#define AI_DATA_ACQUISITION_START			0x14 /*Writing a 1 to start acquisition data.*/
#define READ_WRITE_INTERRUPT_CONTROL_STATUS		0x18
#define CLEAR_INTERRUPT		0x1c	/* Write a 0 to clear PCI interrupt */
#define READ_WRITE_AO_CONTROL_STATUS			0x20
#define READ_WRITE_DIO		0x24
#define READ_WRITE_COUNTER0_CONTROL_STATUS		0x28
#define READ_WRITE_COUNTER0_PERIOD_CONTROL_STATUS	0x2c
#define READ_WRITE_COUNTER1_CONTROL_STATUS		0x30
#define READ_WRITE_COUNTER1_PERIOD_CONTROL_STATUS	0x34
#define READ_CARDID_FIRMWARE_VERSION			0x3c

/* bar 1 */
#define	READ_WRITE_XILINX_SPARTAN6_DMA_CONTROL_STATUS	0x00  /* winson not confirm 0x00~0x04 */

/* abbreviation of registers */
/* bar 0 */
#define	AI_FD	READ_AI_FIFO_DATA
#define	AI_FS	READ_AI_FIFO_STATUS
#define	CF	CLEAR_FIFO
#define RW_ICCS	READ_WRITE_AI_INTERNAL_CLOCK_CONTROL_STATUS  //for AI
#define	RW_AICS	READ_WRITE_AI_MODE_CONTROL_STATUS
#define	AI_L	READ_AI_DATA_LOW  /* channel 0~7 */
#define	AIST	AI_SOFTWARE_TRIGGER_CONTROL
#define	AI_H	READ_AI_DATA_HIGH  /* channel 8~15 */
#define	AI_DAS	AI_DATA_ACQUISITION_START
#define	RW_ICS	READ_WRITE_INTERRUPT_CONTROL_STATUS
#define	CI	CLEAR_INTERRUPT
#define	RW_AOCS	READ_WRITE_AO_CONTROL_STATUS
#define	DIO	READ_WRITE_DIO
#define	CN0CS	READ_WRITE_COUNTER0_CONTROL_STATUS
#define	CN0PCS	READ_WRITE_COUNTER0_PERIOD_CONTROL_STATUS
#define	CN1CS	READ_WRITE_COUNTER1_CONTROL_STATUS
#define	CN1PCS	READ_WRITE_COUNTER1_PERIOD_CONTROL_STATUS
#define	CID	READ_CARDID_FIRMWARE_VERSION

/* bar 1 */
#define	RW_XSDCS	READ_WRITE_XILINX_SPARTAN-6_DMA_CONTROL_STATUS

/* mask of registers (32-bit operation) */
#define AI_FD_MASK	0x0000ffff
#define AI_FS_MASK	0x00001fff
#define CF_MASK		0x00001fff
#define RW_ICCS_MASK	0xffffffff
#define RW_AICS_MASK	0x0000138f
#define AI_L_MASK	0x0000ffff
#define AIST_MASK	0x00000001
#define AI_H_MASK	0x0000ffff
#define AI_DAS_MASK	0x00000003
#define RW_ICS_MASK	0x0000ffff
#define CI_MASK		0x00000001
#define RW_AOCS_MASK	0x01ffffff
#define DIO_MASK	0x0fff0fff
#define CN0CS_MASK	0xffffffff
#define CN0PCS_MASK	0xffffffff
#define CN1CS_MASK	0xffffffff
#define CN1PCS_MASK	0xffffffff
#define CID_MASK	0xffffffff	/* winson not confirm */
#define RW_XSDCS_MASK	0x00000000	/* winson have no idea */

/* XILINX SP6 Series DUAL Port RAM CRC(High Byte) */
static unsigned char CRC16Hi[] = {
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
	0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
};

/* XILINX SP6 Series DUAL Port RAM CRC(Low Byte) */
static unsigned char CRC16Lo[] = {
	0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2,
	0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04,
	0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
	0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8,
	0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A,
	0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
	0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6,
	0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10,
	0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
	0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4,
	0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE,
	0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
	0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA,
	0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C,
	0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
	0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0,
	0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62,
	0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
	0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE,
	0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68,
	0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
	0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C,
	0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76,
	0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
	0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92,
	0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54,
	0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
	0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98,
	0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A,
	0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
	0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86,
	0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40
};

#endif					/* _PCIe8622_H */
