#ifndef _D64H_CPLD_H_
#define _D64H_CPLD_H_

#define NUMBER_OF_DMA_CHANNELS              PCI9054_DMA_CHANNELS     // Total number of DMA Channels
#define PIO_D64H

// DMA channel information 
typedef struct _DMA_CHANNEL_INFO
{
    //DMA_STATE           state;                    // DMA Channel open state
    VOID                *pOwner;                  // Object that requested to open the channel
    BOOLEAN             bLocalAddrConstant;       // Flag to keep track if local address remains constant
    //PIRP                pIrp;                     // Current IRP which requested a DMA
    //PMDL                pSglMdl;                   // Scatter-Gather MDL of the user buffer for locking and unlocking 
    //PCI_MEMORY          SglBuffer;                // Describes SGL buffer information    
    
#if defined(PIO_D64H)     
    U32                 dwTransferSize;           // DO DMA transfer size (bytes)
    U32                 dwPCIAddr;                // Lower 32-bits of PCI address    
    U32                 dwKernelAddr;                // Kernel Space of Block DMA buffer    
    LONG                bDbfMode;                 // Flag to indicate the Double Buffer mode    
    LONG                bLowHalfBufReady;         // Flag to indicate the Low Half Buffer is ready
    LONG                bHighHalfBufReady;        // Flag to indicate the High Half Buffer is ready        
    LONG                bUseHighHalfBuf;          // Flag to indicate the Low/High Half Buffer is being used    
    LONG                bIoctlHighHalfBuf;        // Flag to indicate the Low/High Buffer is required for Half-Ready IOCTL	
    
    LONG                bDMARestart;
    U32                 dwReXferSize;             // DO DMA Re-transfer size (bytes)     
    U32                 dwReXferPCIAddr;          // Lower 32-bits of PCI address     
    
    LONG                bSyncMode;                // SyncMode 
    
    LONG                bFifoLoopCnt;             // defined for pattern-output feature
    U32                 dwPacerValue;
    U32                 dwSplitePacerValue;
    
    LONG                bRunning;  
    
    //PMDL		pBlockMdl;		// The MDL point for Block DMA Buffer    
    ULONG		dwIdx;			// The current Index index in Buffer       
    ULONG		dwLen;			// The total buffer lemgth
    ULONG		dwPA[2];		// The Physical Address of OFFSET Buffer
    PVOID		pVA[2];		  // The Kernel Virtual Address of OFFSET Buffer    
    PVOID		hMapView[2];		// The Map-View for OFFSET Buffer
    
    PVOID		DBEventObject;	      // Events to notify the ocurrence of Interrupt
    PVOID		EndEventObject;	      // Events to notify the End of DMA Operation
		
    //PIRP       		pIrpPending;		// Pointer to recored the pendig-Irp
    PLX_NOTIFY_OBJECT	NotifyObject;
    PLX_NOTIFY_OBJECT	*pNotifyObject;
        
    U16                 wIterations;              // Iterations for DO operation        
    U32                 dwDio_HFul_HEmp_Enable;   // Enable HFul_HEmp flag
    U32                 dwDio_HFul_HEmp_Mask;     // Mask to clear HFul_HEmp flag
    U32                 dwFifoCntrOfst;
    U32                 dwDMADoneMask;

    //KSPIN_LOCK          Lock_CfgSetting;
    
    U32                 dwDpcDioCtlMask;             // DIO_CTRL_REG mask after DMA completion
#endif
        
} DMA_CHANNEL_INFO, *PDMA_CHANNEL_INFO;  

typedef struct _D64H_CPLD_INFO
{
        S32			DevNum;
        PLX_DEVICE_OBJECT	Device;
        PLX_DEVICE_KEY		DevKey_DMA;
        ULONG			dwIntCtrlReg;
        ULONG			dwDioCtrlReg;
        U32			cpldAddress;
	LONG			bWhoUseDMA0;
	DMA_CHANNEL_INFO	DmaInfo[NUMBER_OF_DMA_CHANNELS];
} D64H_CPLD_INFO, *PD64H_CPLD_INFO;
#endif
