#ifndef __REG9054_H
#define __REG9054_H

/*******************************************************************************
 * Copyright (c) 2001 PLX Technology, Inc.
 * 
 * PLX Technology Inc. licenses this software under specific terms and
 * conditions.  Use of any of the software or derviatives thereof in any
 * product without a PLX Technology chip is strictly prohibited. 
 * 
 * PLX Technology, Inc. provides this software AS IS, WITHOUT ANY WARRANTY,
 * EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  PLX makes no guarantee
 * or representations regarding the use of, or the results of the use of,
 * the software and documentation in terms of correctness, accuracy,
 * reliability, currentness, or otherwise; and you rely on the software,
 * documentation and results solely at your own risk.
 * 
 * IN NO EVENT SHALL PLX BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
 * LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
 * OF ANY KIND.  IN NO EVENT SHALL PLX'S TOTAL LIABILITY EXCEED THE SUM
 * PAID TO PLX FOR THE PRODUCT LICENSED HEREUNDER.
 * 
 ******************************************************************************/

/******************************************************************************
 * 
 * File Name:
 *
 *      Reg9054.h
 *
 * Description:
 *
 *      This file defines all the PLX 9054 chip Registers.
 *
 * Revision:
 *
 *      09-31-01 : PCI SDK v3.40
 *
 ******************************************************************************/




#define ULONG unsigned long

//#include "PlxDefinitionsCheck.h"
//#include "PciRegs.h"

#ifdef __cplusplus
extern "C" {
#endif

#define PCI9054_REG_BASE         0x000
#define PCI9054_NEW_CAP_BASE     0x000
#define PCI9054_MAX_REG_OFFSET   0x100



// Additional defintions
#define PCI9054_EEPROM_SIZE          0x058          // EEPROM size (bytes) used by PLX Chip
#define PCI9054_DMA_CHANNELS         2              // Number of DMA channels supported by PLX Chip

// PCI Configuration Registers
#define PCI9054_VENDOR_ID            CFG_VENDOR_ID
#define PCI9054_COMMAND              CFG_COMMAND
#define PCI9054_REV_ID               CFG_REV_ID
#define PCI9054_CACHE_SIZE           CFG_CACHE_SIZE
#define PCI9054_RTR_BASE             CFG_BAR0
#define PCI9054_RTR_IO_BASE          CFG_BAR1
#define PCI9054_LOCAL_BASE0          CFG_BAR2
#define PCI9054_LOCAL_BASE1          CFG_BAR3
#define PCI9054_UNUSED_BASE1         CFG_BAR4
#define PCI9054_UNUSED_BASE2         CFG_BAR5
#define PCI9054_CIS_PTR              CFG_CIS_PTR
#define PCI9054_SUB_ID               CFG_SUB_VENDOR_ID
#define PCI9054_EXP_ROM_BASE         CFG_EXP_ROM_BASE
#define PCI9054_CAP_PTR              CFG_CAP_PTR
#define PCI9054_RESERVED2            CFG_RESERVED1
#define PCI9054_INT_LINE             CFG_INT_LINE
#define PCI9054_PM_CAP_ID            0x040
#define PCI9054_PM_CSR               0x044
#define PCI9054_HS_CAP_ID            0x048
#define PCI9054_VPD_CAP_ID           0x04c
#define PCI9054_VPD_DATA             0x050


// Local Configuration Registers
#define PCI9054_SPACE0_RANGE         0x000
#define PCI9054_SPACE0_REMAP         0x004
#define PCI9054_LOCAL_DMA_ARBIT      0x008
#define PCI9054_ENDIAN_DESC          0x00c
#define PCI9054_EXP_ROM_RANGE        0x010
#define PCI9054_EXP_ROM_REMAP        0x014
#define PCI9054_SPACE0_ROM_DESC      0x018
#define PCI9054_DM_RANGE             0x01c
#define PCI9054_DM_MEM_BASE          0x020
#define PCI9054_DM_IO_BASE           0x024
#define PCI9054_DM_PCI_MEM_REMAP     0x028
#define PCI9054_DM_PCI_IO_CONFIG     0x02c
#define PCI9054_SPACE1_RANGE         0x0f0
#define PCI9054_SPACE1_REMAP         0x0f4
#define PCI9054_SPACE1_DESC          0x0f8
#define PCI9054_DM_DAC               0x0fc


// Runtime Registers

#define PCI9054_MAILBOX0         0x078
#define PCI9054_MAILBOX1         0x07c

#define PCI9054_MAILBOX2             0x048
#define PCI9054_MAILBOX3             0x04c
#define PCI9054_MAILBOX4             0x050
#define PCI9054_MAILBOX5             0x054
#define PCI9054_MAILBOX6             0x058
#define PCI9054_MAILBOX7             0x05c
#define PCI9054_LOCAL_DOORBELL       0x060
#define PCI9054_PCI_DOORBELL         0x064
#define PCI9054_INT_CTRL_STAT        0x068
#define PCI9054_EEPROM_CTRL_STAT     0x06c
#define PCI9054_PERM_VENDOR_ID       0x070
#define PCI9054_REVISION_ID          0x074


// DMA Registers
#define PCI9054_DMA0_MODE            0x080
#define PCI9054_DMA0_PCI_ADDR        0x084
#define PCI9054_DMA0_LOCAL_ADDR      0x088
#define PCI9054_DMA0_COUNT           0x08c
#define PCI9054_DMA0_DESC_PTR        0x090
#define PCI9054_DMA1_MODE            0x094
#define PCI9054_DMA1_PCI_ADDR        0x098
#define PCI9054_DMA1_LOCAL_ADDR      0x09c
#define PCI9054_DMA1_COUNT           0x0a0
#define PCI9054_DMA1_DESC_PTR        0x0a4
#define PCI9054_DMA_COMMAND_STAT     0x0a8
#define PCI9054_DMA_ARBIT            0x0ac
#define PCI9054_DMA_THRESHOLD        0x0b0
#define PCI9054_DMA0_PCI_DAC         0x0b4
#define PCI9054_DMA1_PCI_DAC         0x0b8


// Messaging Unit Registers
#define PCI9054_OUTPOST_INT_STAT     0x030
#define PCI9054_OUTPOST_INT_MASK     0x034
#define PCI9054_MU_CONFIG            0x0c0
#define PCI9054_FIFO_BASE_ADDR       0x0c4
#define PCI9054_INFREE_HEAD_PTR      0x0c8
#define PCI9054_INFREE_TAIL_PTR      0x0cc
#define PCI9054_INPOST_HEAD_PTR      0x0d0
#define PCI9054_INPOST_TAIL_PTR      0x0d4
#define PCI9054_OUTFREE_HEAD_PTR     0x0d8
#define PCI9054_OUTFREE_TAIL_PTR     0x0dc
#define PCI9054_OUTPOST_HEAD_PTR     0x0e0
#define PCI9054_OUTPOST_TAIL_PTR     0x0e4
#define PCI9054_FIFO_CTRL_STAT       0x0e8


// PCI9054_EEPROM_CTRL_STAT (0x6C)
#define PCI9054_SOFTWARE_RESET            0x40000000
#define PCI9054_SOFTWARE_RESET_MACK     (~0x40000000)


// PIO-D64H CPLD registers 
//#define D64H_BYTES_PER_DATA             4  // 32-bits
#define D64H_BITS_SHIFT_PER_SAMPLE        2  // 32-bits

#define D64H_DI_FIFO_SIZE                 1024 // 1K samples
#define D64H_DO_FIFO_SIZE                 2048 // 2K samples 

#define PIOD64H_REG_BASE							   0x00

#define PIOD64H_TIMER0_CNTR_REG         (PIOD64H_REG_BASE + 0x000)
#define PIOD64H_TIMER1_CNTR_REG         (PIOD64H_REG_BASE + 0x004)
#define PIOD64H_TIMER2_CNTR_REG         (PIOD64H_REG_BASE + 0x008)

#define PIOD64H_DI_REG                  (PIOD64H_REG_BASE + 0x010)
#define PIOD64H_DO_REG                  (PIOD64H_REG_BASE + 0x014)

#define PIOD64H_DIO_CTRL_REG            (PIOD64H_REG_BASE + 0x018)
#define PIOD64H_INT_CTRL_REG            (PIOD64H_REG_BASE + 0x01c)
#define PIOD64H_PT_REG                  (PIOD64H_REG_BASE + 0x024)
#define PIOD64H_DI_FIFO_CNTR            (PIOD64H_REG_BASE + 0x028)
#define PIOD64H_DO_FIFO_CNTR            (PIOD64H_REG_BASE + 0x02c)
#define PIOD64H_FIFO_CTRL_REG           (PIOD64H_REG_BASE + 0x030)
#define PIOD64H_DIG_FLT_REG             (PIOD64H_REG_BASE + 0x034)
#define PIOD64H_FIFO_LOOP_CNTR          (PIOD64H_REG_BASE + 0x038)
#define PIOD64H_MISC_REG                (PIOD64H_REG_BASE + 0x03c)

#define PIOD64H_DI_LOCAL_ADDRESS        0x00000100
#define PIOD64H_DO_LOCAL_ADDRESS        0x00000100

#define INT_O_ACK_ACTIVE                0x00000020
#define INT_I_REQ_ACTIVE                0x00000040
#define INT_TIMER0_ACTIVE               0x00000080
#define INT_TIMER1_ACTIVE               0x00000100
#define INT_TIMER2_ACTIVE               0x00000200


//#define INT_DIO_FIFO_HALF_EMPTY         0x01000000
#define DI_FILTER_COUNT_SHIFT           0
#define IREQ_FILTER_COUNT_SHIFT         7
#define OACK_FILTER_COUNT_SHIFT         14
#define ITRG_FILTER_COUNT_SHIFT         21
#define OREQ_PULSE_WIDTH_SHIFT          28


#define DI_FILTER_COUNT_MASK            0xFFFFFF80
#define IREQ_FILTER_COUNT_MASK          0xFFFFC07F
#define OACK_FILTER_COUNT_MASK          0xFFE03FFF
#define ITRG_FILTER_COUNT_MASK          0xF01FFFFF
#define OREQ_PULSE_WIDTH_MASK           0x8FFFFFFF


#define INVALID_MASK                    0xFFFFFFFF

// MISC_REG 0x03C
#define DMA0_OWNERSHIP_MASK           (~0x00010000)
#define OACK_EDGE_TRIGGER_MASK        (~0x00000010)
#define TIMER_CLOCK_DIVIDER_MASK      (~0x00F00000)

//#define OACK_FALL_EDGE_TRIGGER          0x00000000
//#define OACK_RISING_EDGE_TRIGGER        0x00000010

#define OACK_FALLING_EDGE_TRIGGER       0x00000010
#define OACK_RISING_EDGE_TRIGGER        0x00000000

#ifdef _10MHz_BASE_CLOCK_
#define CLOCK_DIVIDER_10MHZ             0x00100000
#endif

// DIO_CTL_REG 0x018
#define PIOD64H_DIO_IGNORE_MASK       (~0x00014000) // DI_OVER & DO_UND are exclusive
#define PIOD64H_DI_CONFIG_MASK        (~0x0001407F) // DI_OVER, DO_UND & B6 ~ B0 are exclusive
#define PIOD64H_DO_CONFIG_MASK        (~0x00014F80) // DI_OVER, DO_UND & B11 ~ B7 are exclusive

#define PIOD64H_DO_EXT_TRIG_MASK      (~0x00014800) // DI_OVER, DO_UND & O_TRG are exclusive
#define PIOD64H_DO_EXT_TRIG_HIGH        0x00000800

#define PIOD64H_DI_OVERRUN_MASK         0x00004000
#define PIOD64H_DO_UNDERRUN_MASK        0x00010000

#define PIOD64H_DI_TIMER_ENABLE         0x00000004
#define PIOD64H_DI_FIFO_ENABLE          0x00000008

#define PIOD64H_DO_TIMER_ENABLE         0x00000200
#define PIOD64H_DO_FIFO_ENABLE          0x00000400

#define PIOD64H_DI_FIFO_TIMER_MASK    (~0x0001400C) // DI_OVER, DO_UND, DI_FIFO_EN & TIMER0_EN are exclusive
#define PIOD64H_DO_FIFO_TIMER_MASK    (~0x00014600) // DI_OVER, DO_UND, DO_FIFO_EN & TIMER1_EN are exclusive

#define PIOD64H_DI_FIFO_TIMER_ENABLE  ( PIOD64H_DI_TIMER_ENABLE | PIOD64H_DI_FIFO_ENABLE )
#define PIOD64H_DO_FIFO_TIMER_ENABLE  ( PIOD64H_DO_TIMER_ENABLE | PIOD64H_DO_FIFO_ENABLE )

// INT_CTL_REG 0x01C
//#define INT_CTL_REG_FLAG_MASK         (~0x010003E0)
#define INT_CTL_REG_FLAG_MASK         (~0x000003E0) // B9 ~ B5 are exclusive

#define PIOD64H_TIMER0_CASCADED_MASK	(~0x000007E0) // TIMER0_Cascad & B9 ~ B5 are exclusive
#define PIOD64H_TIMER1_CASCADED_MASK	(~0x00000BE0) // TIMER1_Cascad & B9 ~ B5 are exclusive

#define PIOD64H_TIMER0_CASCADED_ENABLE	0x00000400
#define PIOD64H_TIMER1_CASCADED_ENABLE	0x00000800

#define PIOD64H_REQ_NEG_MASK          (~0x000013E0) // REG_NEG & B9 ~ B5 are exclusive
#define PIOD64H_I_REQ_FALLING_EDGE      0x00001000

// FIFO_CTL_REG 0x030
#define PIOD64H_DO_FIFO_EMPTY_FLAG      0x00000001
#define PIOD64H_DI_FIFO_EMPTY_FLAG      0x00010000
#define PIOD64H_DI_FIFO_AEMPTY_FLAG     0x00100000
#define PIOD64H_DI_FIFO_AEMPTY_MASK     0x00110000

//#define PIOD64H_DO_HALF_EMPTY_ENABLE    0x00000200
#define PIOD64H_DO_HALF_EMPTY_DISABLE_MASK (~0x00000200)
#define PIOD64H_DO_HALF_EMPTY_ENABLE    0x00000300
#define PIOD64H_DO_HALF_EMPTY_MASK      0x00000400
#define PIOD64H_DO_FIFO_RESET           0x00008000
#define PIOD64H_DO_FIFO_RESET_MASK    (~0x00008000)

//#define PIOD64H_DI_HALF_FULL_ENABLE     0x02000000
#define PIOD64H_DI_HALF_FULL_DISABLE_MASK   (~0x02000000)
#define PIOD64H_DI_HALF_FULL_ENABLE     0x03000000
#define PIOD64H_DI_HALF_FULL_MASK       0x04000000
#define PIOD64H_DI_FIFO_RESET           0x80000000
#define PIOD64H_DI_FIFO_RESET_MASK    (~0x80000000)

#define PIOD64H_DIO_FIFO_CTL_REG_MASK (~0x85008500)

//#define PIOD64H_DI_DMA_ENABLE_MASK    (~0x00000001)
//#define PIOD64H_DO_DMA_ENABLE_MASK    (~0x00000100)
//#define PIOD64H_DI_DMA_STATUS_MASK      0x00000011
//#define PIOD64H_DO_DMA_STATUS_MASK      0x00001100
//#define PIOD64H_DI_DMA_ENABLE           0x00000001
//#define PIOD64H_DO_DMA_ENABLE           0x00000100
//#define PIOD64H_DI_DMA_DONE             0x00000010
//#define PIOD64H_DO_DMA_DONE             0x00001000
//#define PIOD64H_DI_DMA_ABORT            0x00000004
//#define PIOD64H_DO_DMA_ABORT            0x00000400

#define PIOD64H_DMA_CHAN0_ENABLE_MASK (~0x00000001)
#define PIOD64H_DMA_CHAN1_ENABLE_MASK (~0x00000100)

#define PIOD64H_DMA_CHAN0_STATUS_MASK   0x00000011
#define PIOD64H_DMA_CHAN1_STATUS_MASK   0x00001100

#define PIOD64H_DMA_CHAN0_ENABLE        0x00000001
#define PIOD64H_DMA_CHAN1_ENABLE        0x00000100

#define PIOD64H_DMA_CHAN0_DONE          0x00000010
#define PIOD64H_DMA_CHAN1_DONE          0x00001000

#define PIOD64H_DMA_CHAN0_ABORT         0x00000004
#define PIOD64H_DMA_CHAN1_ABORT         0x00000400


//#define PIOD64H_MAX_DI_SAMPLES_IN_FIFO  0x010 //  16 Samples
//#define PIOD64H_MAX_DO_SAMPLES_IN_FIFO	0x100 // 256 Samples
//#define PIOD64H_MAX_DI_SAMPLES_IN_FIFO_MOD_MASK  0x00F //  0~15 Samples
//#define PIOD64H_MAX_DO_SAMPLES_IN_FIFO_MOD_MASK  0x0FF //  0~255 Samples

#define PIOD64H_DI_USE_DMA0             0x00000000L
#define PIOD64H_DO_USE_DMA0             0x00010000L

#pragma pack(push,1)

typedef union {
	struct {
		ULONG	I_ACK	: 1;
		ULONG	I_REQ	: 1;
		ULONG	I_TIME0	: 1;
		ULONG	I_FIFO	: 1;
		ULONG	TRGPOL	: 1;
		ULONG	W_TRG	: 1;
		ULONG	DIN_EN	: 1;
		ULONG	O_ACK	: 1;
		ULONG	O_REQ	: 1;
		ULONG	O_TIME1	: 1;
		ULONG	O_FIFO	: 1;
		ULONG	O_TRG	: 1;
		ULONG	BIT12_13	: 2;
		ULONG	I_OVR	: 1;
		ULONG	BIT15	: 1;
		ULONG	O_UND	: 1;
		ULONG	BIT17_31	: 15;
		} diocsr;
	struct {
		ULONG	DIMS	: 7;
		ULONG	DOMS	: 5;
		ULONG	BIT12_13	: 2;
		ULONG	I_OVR	: 1;
		ULONG	BIT15	: 1;
		ULONG	O_UND	: 1;
		ULONG	BIT17_31	: 15;			
		} diomsk;		
	ULONG r;
} DIO_CTL_REG;


typedef union {
	struct {
		ULONG	IO_ACK	: 1;
		ULONG	II_REQ	: 1;
		ULONG	T0_EN	: 1;
		ULONG	T1_EN	: 1;
		ULONG	T2_EN	: 1;
		ULONG	SO_ACK	: 1;
		ULONG	SI_REQ	: 1;
		ULONG	SI_T0	: 1;
		ULONG	SI_T1	: 1;
		ULONG	SI_T2	: 1;
		ULONG	T0_T2	: 1;
		ULONG	T1_T2	: 1;
		ULONG	REQ_NEG	: 1;
		ULONG	BIT13_23 : 11; 
		ULONG	DO_FIFO_HALF_EMPTY :1; // write one to clear
		ULONG	BIT25_31 :7;
		} intcsr;
	struct {
		ULONG	IT_CTRL	: 5;
		ULONG	IT_STAT	: 5;
		ULONG	TC_CTRL : 2;
		ULONG	REQ_NEG : 1;
		ULONG	BIT13_23 : 11; 
		ULONG	DO_FIFO_HALF_EMPTY :1; // write one to clear
		ULONG	BIT25_31 :7;			
		} intmsk;		
	ULONG r;
} INT_CTL_REG;

#pragma  pack(pop)


// Event type for the event message

#define DIEnd       0
#define DOEnd       0
#define DBEvent     1
#define TrigEvent   2

//Clock Mode
#define TRIG_SOFTWARE           0
#define TRIG_INT_PACER          1
#define TRIG_EXT_STROBE         2
#define TRIG_HANDSHAKE          3

#define TIMER_INDIVIDUAL        0
#define TIMER_CASCADE_NEEDED    1

/*-------- Constants for PCI-7200 --------------------*/
//InputMode
#define DI_WAITING              0x02
#define DI_NOWAITING            0x00

#define DI_TRIG_RISING          0x04
#define DI_TRIG_FALLING         0x00

#define IREQ_RISING             0x08
#define IREQ_FALLING            0x00

//Output Mode
#define OREQ_ENABLE             0x10
#define OREQ_DISABLE            0x00

#define OTRIG_HIGH              0x20
#define OTRIG_LOW               0x00

// Function Index -- AI, AO, DI, DO
#define	PLX9054_DMA_CHAN0			  0
#define	PLX9054_DMA_CHAN1			  1

#define DAQ_OPERATION_DI       0
#define DAQ_OPERATION_DO       1

#define DOUBLE_BUFFER_MODE_ENABLE		0x01
#define DOUBLE_BUFFER_MODE_DISABLE	0x00

//Synchronous Mode
#define SYNCH_OP                                  0x01
#define ASYNCH_OP                                 0x02

#ifdef __cplusplus
}
#endif

#endif
